Copper metallization is increasingly being used for advanced semiconductor device integrated circuit fabrication including semiconductor features having sub-quarter micron linewidths and high aspect ratios to larger features such as bonding pads. Copper and its alloys have lower resistivity and better electromigration resistance compared to other metals such as, for example, aluminum. These characteristics are critical for achieving device reliability together with higher current densities and increased signal propagation speed. While several processing difficulties related to forming copper semiconductor features have been overcome, several problems remain, including the problem of barrier layer coverage and integrity to prevent copper migration as well as reducing signal delay caused by capacitive contributions of etch stop and barrier layers in a multi-layered integrated circuit.
One increasing problem with prior art methods of forming copper dual damascenes including barrier layers is achieving adequate coverage of the barrier layers over both the via and trench line portions of the dual damascene structure. For example as device critical dimensions shrink below about 1.0 microns and aspect ratios of vias increase to greater than about 4.5, the barrier layer coverage in the trench line portion is increasingly limited by the coverage of the via portion. For example, as the aspect ratio of the via increases to greater than about 3.5, the step coverage of the barrier layer rapidly decreases, especially along the sidewalls of the damascene opening. As a result, the probability for copper migration under moderate temperatures and electrical fields increases to unacceptable values, degrading device performance and reliability.
Moreover, as device sizes decrease the impact of capacitive contributions from barrier layers and etch stop layer increases, creating a tension between the goals of forming reliable and effective copper diffusion barriers and etch stop layers while reducing the capacitive contribution of such layers.
Thus, there is a continuing need for novel semiconductor device integrated circuit manufacturing methods to improve the electrical performance of metal interconnect features including improved etch stop layer and barrier layer integrity and performance while reducing a capacitive contribution to signal propagation delay.
It is therefore among the objects of the invention to provide a method to improve the reliability and electrical performance of metal interconnect features including improved etch stop layer and barrier layer integrity and performance while reducing a capacitive contribution to signal propagation delay, in addition to overcoming other shortcomings of the prior art.